1. Field of the Invention
The present invention relates generally to the field of semiconductor devices. More particularly, the present invention relates to RF/millimeter-wave (mmW) transistor device structure and layout thereof.
2. Description of the Prior Art
The rapid scaling of CMOS to shorter channel lengths has enabled circuits to operate well into the millimeter-wave frequency range. While CMOS is not an obvious technology for millimeter-wave applications in terms of raw performance, especially compared to SiGe and III-V technologies, it has clear advantages including low cost and potential for integration with other parts of the system which makes it a natural candidate for exploration.
It has been known that the device layout impacts on the device performance in mm-wave frequencies. Unlike low-frequency circuit design in which the device design is absolutely in the realm of process engineers, the device performance may be altered drastically by changing the device layout. This enables the circuit designers to layout the device based on the performance metric appropriate to a specific application. For instance, fmax, which is an indicator of the speed of the transistor, has been reported to vary from 80 GHz to up to 280 GHz for an identical CMOS 90 nm process, mainly due to differences in the layout. It also has been known that the gate-to-drain capacitance (Cgd) and the gate resistance (Rg) have the largest impact on fmax.
For example, some common performance metrics for mm-wave devices include fmax, transit frequency (fT), maximum stable gain (MSG), maximum unilateral gain (U), output power, drain efficiency, and minimum noise factor Fmin. The selection of the appropriate metric as an optimization target depends on the specific application of the device. It has been found that the source resistance changes the MSG since it changes the effective transconductance through its local feedback effect. Generally, lower source resistance (Rs) results in lower noise for low-noise amplifier (LNA), higher power gain for both LNA and power amplifier (PA), and higher efficiency for PA. Lower Rg results in lower noise for LNA, while lower drain resistance Rd results in higher efficiency for PA.
“Millimeter-Wave Devices and Circuit Blocks up to 104 GHz in 90 nm CMOS”, IEEE journal of Solid-State Circuits, Vol. 42, No. 12, December 2007, Pages 2893-2903, by B. Heydari, M. Bohsali, E. Adabi, and A. M. Niknejad, discloses a multi-finger layout of a 80*1 μm/90 nm NMOS device and claims that such device layout increases the fmax up to 20% and renders the MSG unchanged. However, the aforesaid device layout has drawbacks including high Rg due to single side gate contacts, large gate-to-bulk or drain-to-bulk capacitance that in turn lowers fT and fmax, and large distributed Rd, Rs and Rg due to long metal traces.
The above-mentioned reference also discloses a round-table NMOS device comprising a plurality of sub-cells arranged in a circularly connecting (round-table) configuration. However, the round-table device has drawbacks including large overall aspect ratio and large distributed Rd, Rs and Rg due to long metal traces. Besides, the round-table device requires rotation of the sub-cells leading to different direction of the gate fingers, which is difficult to practice in the advanced process.